A flash memory device is a type of a nonvolatile memory device being capable of retaining data with a power supply cut off, and is a highly-integrated device made using an EPROM (erasable programmable read only memory) and an EEPROM (electrically erasable programmable read only memory).
A conventional flash memory cell has a stack-gate structure including a tunnel oxide layer, a floating gate, an insulating layer, and a control gate, which are stacked on a semiconductor substrate between a source and a drain.
One drawback associate with the stack-gate structure is an over-erase phenomenon, and as one of the efforts to solve the problem, there has been introduced a flash memory cell having a split gate structure. Japanese Laid Open Disclosure No. 1999-284084, entitled, “Nonvolatile Semiconductor Memory Device and its Manufacture,” by Otani Toshiharu, discloses a method of fabricating a split gate using a local oxidation of silicon (LOCOS) process.
FIGS. 1A to 1E illustrate in detail a method of fabricating a flash memory cell having a split gate structure in accordance with prior art.
As shown in FIG. 1A, a gate oxide layer 11, a first polysilicon layer 12, and a silicon nitride layer 13 are stacked on a semiconductor substrate 10.
Then, as shown in FIG. 1B, by patterning the silicon nitride layer 13, there is formed a silicon nitride layer pattern 13A having an opening 13B therein, exposing a portion of the first polysilicon layer 12.
Then, as shown in FIG. 1C, a poly oxide layer 14 is formed by performing a LOCOS process using the silicon nitride layer pattern 13A as an oxidation stop layer so as to oxidize a portion of the exposed first polysilicon layer 12.
Then, as shown in FIG. 1D, a floating gate 12A is formed under the poly oxide layer 14 by removing the silicon nitride layer pattern 13A and etching the first polysilicon layer 12 using the poly oxide layer 14 as an etch mask.
Then, as shown in FIG. 1E, an oxide layer 15 is formed on the semiconductor substrate 10 and the poly oxide layer 14, and then, a control gate 16 overlapping a portion of the floating gate 12A is formed of a second polysilicon layer. Then, the processes of forming spacers 17 on the sidewalls of the floating gate 12A and the control gate 16, and forming source/drain 18A, 18B inside the semiconductor substrate 10, and the like are performed. The oxide layer 15 functions as a tunnel oxide layer 15A in the region between the floating gate 12A and the control gate 16, and functions as a gate oxide layer 15B in the region between the semiconductor substrate 10 and the control gate 16.
However, the LOCOS process in the conventional method of fabricating a flash memory cell having a split gate structure described above has a difficulty in forming the poly oxide layer 14, being formed for the insulation between the floating gate 12A and the control gate 16, with a uniform thickness. Further, the LOCOS process has some other drawbacks such as causing a heat budget due to the thermal oxidation performed at a temperature of about 800° C., and a smiling effect on the boundary of the gate oxide layer to be thickened. Therefore, the degradation of cell characteristics may result, and malfunctioning may happen during programming and erasing operations.
Many parasitic capacitors exist in the flash memory cell having the split gate structure fabricated by the method in accordance with the conventional approach described above. Referring to FIG. 1E, there exists a tunnel capacitor (Ct) between the sidewalls of the control gate 16 and the floating gate 12A, and there exists a gate interlayer capacitor (Cip) between the control gate 16 and the upper surface of the floating gate 12A. Further, there exists a channel capacitor (Cc) between the floating gate 12A and the semiconductor substrate 10, and there exists a source capacitor (Cs) between the floating gate 12A and the source 18A.
In programming the flash memory cell having the split gate structure as shown in FIG. 1E, a high voltage is applied on the source 18A, and a grounding voltage is applied on the drain 18B. The electrons generated in the drain 18B move to the source 18A through the channel region formed in the semiconductor substrate 10 by the program voltage applied on the control gate 16. The program voltage is lower than the voltage applied on the source 18A and higher than the threshold voltage for the formation of the channel region. Some of the electrons being moved to the source 18A are excited by the potential difference between the drain 18B and the floating gate 12A coupled by the high voltage applied on the source 18A, and are injected into the floating gate 12A. That is, the program operation is performed by a hot carrier injection to the floating gate 12A.
In this case, a program coupling ratio (rp) can be represented by Equation 1 as follows:
                              r          p                =                              C1            +            C2                                C1            +            C2            +            C3            +            C4                                              [                  Equation          ⁢                                          ⁢          1                ]            
In Equation 1, ‘C1’, ‘C2’, ‘C3’, and ‘C4’ are the capacitance of the source capacitor (Cs), the capacitance of the channel capacitor (Cc), the capacitance of the tunnel capacitor (Ct), and the capacitance of the gate interlayer capacitor (Cip), respectively.
Further, in erasing the flash memory cell having the split gate structure, if a high voltage is applied on the control gate 16, and grounding voltages are applied on the source 18A and the drain 18B, the electrons charged in the floating gate 12A are removed to the control gate 16 by the high voltage applied on the control gate 16, that is, the electrons charged in the floating gate 12A are erased by the F-N (Fowler-Nordheim) tunneling effect.
In this case, an erase coupling ratio (rE) can be represented by Equation 2 with the capacitances (C1, C2, C3, C4) of the parasitic capacitors (Cs, Cc, Ct, Cip) as follows:
                              r          E                =                              C3            +            C4                                C1            +            C2            +            C3            +            C4                                              [                  Equation          ⁢                                          ⁢          2                ]            
The width ‘W’ of the poly oxide layer 14 is reduced with the increase in integration of the device. That is, as shown in FIG. 1B, when the width of the exposed polysilicon layer 12 is reduced, the width of the opening 13B, provided for the formation of the poly oxide layer 14, is reduced, and so, the thickness of the poly oxide layer 14, produced by the LOCOS process, is reduced. The reduction of the thickness of the poly oxide layer 14 increases the capacitance of the gate interlayer parasitic capacitor (Cip) between the control gate 16 and the floating gate 12A, thereby resulting in degradation of the device characteristics. That is, if the capacitance of the gate interlayer capacitor (Cip), generated between the floating gate 12A and the control gate 16, is increased, the voltage, applied on the floating gate 12A during programming, is reduced, thereby resulting in decreasing the program efficiency.